A Field Programmable Gate Array (FPGA) or logic device is an integrated circuit, consisting of programmable logic blocks and programmable routing. Programmable logic blocks may include blocks of logic elements, for performing programmable logic operations, and block Random Access Memories (RAMs) for storing and retrieving data. In an illustrative example, block RAMs may contain 16,000 (16K) bits addressable in various address depth and word width configurations. For example, a 16K block RAM may be addressable in a 8×2K configuration, i.e., 8 address locations of 2,000 bits each, or a 1×16K configuration, i.e., 1 address location of 16,000 bits.
Block RAMs may receive inputs from address ports and data ports. Each block RAM may have two address ports and two data ports—one address port and one data port for reading and one address port and one data port for writing.
If wide data ports, i.e., data ports capable of processing a large number of data bits, or deeper address ports, i.e., address ports capable of processing a large number of address locations, are required, then multiple blocks RAMs may be accessed in parallel. For example, each block RAM in a group of multiple block RAMs may provide some portion of the desired data or address ports. Thus, a group of multiple block RAMs may be physically stitched together to form a virtual large block RAM. Virtual large block RAMs may be used to implement, for example, wide First-In-First-Out (FIFO) queues, wide memories, and/or data-burst accessible block RAMs.
In conventional implementations of such group block RAMs, address lines have to be routed to each block RAM in the group of block RAMs. Additional soft logic may be required to create a local address for each block RAM when implementing byte-addressable wide memories. Group block RAMs used to implement wide FIFOs would also require multiple address lines to be routed to each block RAM in the group of block RAMs. Routing address lines consumes general interconnect resources, which are limited, and the toggling of the address lines in the general interconnect adds to overall power consumption. Additionally, routing address lines often results in routing congestion causing critical timing delays in the design being implemented within an FPGA.
This disclosure relates to systems and methods for reducing or eliminating address lines that need to be routed to multiple related embedded memory blocks.